1. Field of the Invention
The present invention relates generally to operation of power transistors in fast switching environments, and relates more particularly to maintaining a power FET in an off condition through current and voltage spikes.
2. Description of Related Art
Power FETs are often used in power control applications due to their low on resistance and reasonably fast switching times. Power FETS are often configured in a totem pole or half bridge arrangement to control power supplied to an output based on a given DC power input. A standard configuration is illustrated in circuit 10 in FIG. 1. This traditional switching output stage can be composed of N type DMOS power FETS, where the highs and low side power FETs 12,13, respectively, alternately switch output node OUT between VDD and GND. FETs 12, 13 are also controlled by drivers 14, 15 that are powered by batteries or power supplies BAT1 and BAT2. The switching configuration where both power FETs 12 and 13 are turned on at the same time is avoided in the operation of circuit 10 to prevent a large current flow between VDD and GND. If both power FETS 12 and 13 are on at the same time, circuit 10 dissipates a large amount of power, sinks a large amount of current and eventually causes power FETs 12 or 13 to fail. This type of undesirable condition when power FETs 12 and 13 are both on is often called shoot through or cross-conduction current.
Due to loading characteristics or other circuit considerations, power FETs 12 and 13 often experience voltage and/or current spikes that may cause disruption in the operation of circuit 10. FIG. 2 illustrates a simplified equivalent circuit of driver 15 as seen by the gate of power FET 13 in an off state. A pulldown equivalent resistance Rn keeps Vgs below the threshold voltage of power FET 13. The output OUT typically has a fast rising edge, which is capacitively coupled, due to the large gate-drain capacitance, to the gate of power FET 13. The capacitive coupling with the fast switching causes voltage spikes to be seen at the gate of power FET 13, as illustrated in FIG. 2. As the equivalent pulldown resistance is small, or weak, the voltage spike on voltage Vgs caused during output voltage swing or fast switching has a negative impact on the operation of power FET 13. If the voltage spike causes gate voltage Vgs to go above the threshold for power FET 13 turn on, voltage Vt, a false turn on of power FET 13 occurs. In such an instance, if power FET 12 is on at the same time, shoot through or cross-conduction current can occur in circuit 10.
When both power FETS 12 and 13 are off, a DC current source connected at output node OUT insures that the output stays low as long as power FETS 12 and 13 are off. If high side power FET 12 is turned on, output OUT rises to a given voltage level, and intrinsic capacitance CGD pulls the voltage of the gate of low side power FET 13 to a level that depends upon the equivalent pull down strength. If the pull down on the gate of low side power FET 13 is weak, such that gate voltage VL or Vgs is equal to or greater than voltage Vt, that is, equal to or greater than the turn on threshold, a large current to GND is observed. The false turn on that results sinks current to GND in the range of a few amps during this output swing.
If the gate of low side power FET 13 is pulled down strongly, low side power FET 13 stays off during the output swing. Low side power FET 13 stays off because gate voltage VL does not rise above threshold voltage Vt.
One advantage to having a weak pull down on the gate of low side power FET 13 is the reduction of EMI or voltage spikes across low side power FET 13. Accordingly, it would be desirable to provide a way to prevent low side power FET 13 from inadvertently turning on, while obtaining the advantages of reduced EMI and noise. It would also be desirable to avoid false turn ons of a power FET in a half bridge configuration, such as that illustrated in circuit 10.